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This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35 mum BiCMOS process. The ADC has an input switched buffer and 11 pipeline stages. The sample-and-hold circuit is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier. Measured results on(More)
Carrier frequency offset (CFO) is an important problem in multi-input multi-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems. This letter proposes a blind CFO estimator for MIMO-OFDM systems with constant modulus constellations in the frequency-selective fading channels. A closed-form CFO estimate is also provided, which greatly reduces(More)