Louise Trevillyan

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As high-level synthesis techniques gain acceptance among designers, it is important to be able to provide a robust system which can handle large designs in short execution times, producing high-quality results. Scheduling is one of the most complex tasks in high-level synthesis, and although many algorithms exist for solving the scheduling problem, it(More)
14 0740-7475/04/$20.00 © 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers WITH AGGRESSIVE SCALING of transistor channel lengths, interconnect delay increasingly dominates chip performance in deep-submicron designs. In addition, the traditional metrics of area and delay are no longer sufficient to ensure successful(More)
A logic designer today faces a growing number of design requirements and technology restrictions, brought about by increases in circuit density and processor complexity. At the same time, the cost of engineering changes has made the correctness of chip implementations more important, and minimization of circuit count less so. These factors underscore the(More)
A new method for optimizing digital logic networks is described. Techniques of data flow analysis are used to summarize a circuit efficiently; this summary is used to characterize a class of circuits which are equivalent to the given circuit, and an algorithm is described which reduces the problem of finding small circuits in this equivalence class to the(More)
Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today’s billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given(More)
This correspondence concerns applications of optimization techniques based on global flow analysis to the automated design of logic. Manuscript received February 17, 1984. The authors are with IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. IEEE Log Number 8406288. 0018-9340/86/0100-0077$01.00 X 1986 IEEE rs out Irs in