Long-Ching Yeh

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In this paper we report a set of statistical static timing (SSTA) studies performed on a UMC test chip manufactured at 90nm process node. We employed comprehensive variation extraction techniques to prepare a complete set of input variation data for the technology node. Our studies include SSTA runs in the presence of various process variation components,(More)
In this paper, we propose a power converter synthesis design flow aimed at SOC applications. A buck DC-DC converter and a low dropout (LDO) linear regulator, both with controllers are studied. We apply both the knowledge-based and the simulation-based methods in the proposed flow and they lead to an accurate result when it is compared with the design(More)
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