Lo-Mei Chang

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For H.264/AVC decoder system, the motion compensation bandwidth comes from two parts, the reference data loading bandwidth and the equivalent bandwidth from DRAM access overhead latency. In this paper, a bandwidth-efficient cache-based MC architecture is proposed. It exploits both intra-MB and inter-MB data reuse and reduce up to 46% MC bandwidth compared(More)
To support these applications, the worldwide first video decoder that supports three most advanced video coding standards – H.264/AVC High Profile, multiview video coding (MVC), and scalable video coding (SVC), is realized. Three main design challenges are encountered. 1) Conventional block-pipelining scheduling and architecture cannot efficiently support(More)
In the process of scalable video coding (SVC) decoding, large external memory bandwidth is required for SVC inter-layer prediction. In this paper, a low bandwidth decoder framework is proposed for SVC. Two main decoding schemes are developed to reduce the external memory bandwidth. Macroblock-level on-the-fly padding and on-line upsampling is proposed for(More)
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