Litvinova Eugenia

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The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is(More)
This article describes logical analysis infrastructure of associative tables (matrices), which enables to perform processing the interaction of the input vector with n-dimensional algebra-logical space, specified by using the ordered and structured tables of problem-oriented data, which represent the associative behavioral models of logical objects. To(More)
This article describes algebra for logical analyzing of vector and tabular forms of information representation to solve the problems of information retrieval, diagnosis, pattern recognition and decision-making in the vector discrete Boolean space. The high-speed models and methods for concurrent vector logical analysis of information, which completely(More)
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