Lirida A. B. Naviner

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0026-2714/$ see front matter 2008 Elsevier Ltd. A doi:10.1016/j.microrel.2008.07.002 * Corresponding author. Address: Institut TELECO CNRS, COMELEC Departement, 46 Rue Barrault, 75 0145817103; fax: +33 0145804036. E-mail address: denis.teixeira@telecom-paristech.f As integrated circuits scale down into nanometer dimensions, a great reduction on the(More)
Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context we introduce a cost-aware methodology for selective hardening of combinational logic cells. The methodology is based(More)
Concurrent error detection (CED) schemes are becoming essential features in the design process as IC technologies progress into the nanoscale era. Soft error rate reduction has emerged as an important challenge and several works are dedicated to quantify the CED effective enhancement in systems reliability. However, none of them make a comprehensive(More)
This paper presents a robust OxRAM-based nonvolatile flip-flop (NVFF) solution, designed for deep nano-scaled CMOS technologies. Forming, set and reset operations rely on a reliable design approach using thin gate oxide CMOS. The NVFF is benchmarked against a standard FF in 28nm CMOS FDSOI. Non-volatility is added with minimal impact on the FF performances.
With the shrinking of dimensions, not only the attacks but also transient faults became important concerns of cryptographic processors based on deep submicron technologies. Fault tolerance is achieved by adding redundancy (area, time and information). Motivated by the need of effective designs, we propose a method to characterize the efficiency of(More)
0026-2714/$ see front matter 2011 Elsevier Ltd. A doi:10.1016/j.microrel.2011.06.020 ⇑ Corresponding author. Tel.: +33 145817333; fax: E-mail addresses: tian.ban@telecom-paristech.fr ( om-paristech.fr (L. Naviner). Redundancy techniques are widely used to increase the reliability of the circuits. This paper proposes an efficient method to select the best(More)