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We present HYBRO, an automatic methodology to generate high coverage input vectors for Register Transfer Level (RTL) designs based on branch-coverage directed approach. HYBRO uses dynamic simulation data and static analysis of RTL control flow graphs (CFGs). A concrete simulation is applied over a fixed number of cycles. Instrumented code records the(More)
Automatic assertion generation methodologies based on machine learning generate assertions at bit level. These bit level assertions are numerous, making them unreadable and frequently unusable. We propose a methodology to discover word level features using static and dynamic analysis of the RTL source code. We use discovered word level features for the(More)
We enhance STAR, an automatic technique for functional input vector generation for design validation. STAR statically analyzes the source code of the Register-Transfer Level (RTL) design. The STAR approach is a hybrid between RTL symbolic execution and concrete simulation that offsets the disadvantages of both. The symbolic execution, which follows the(More)
These years, wireless sensor network (WSN) has emerged as an especially hot topic, which is the result of rapid advances in miniaturization, low-power circuit design, more energy-efficient wireless communication, improved small-scale energy supplies and reduced manufacturing costs. A WSN node consists of four basic components: sensing, data processing,(More)
OBJECTIVE Polymorphisms in the adiponectin gene (ADIPOQ) have been associated with type 2 diabetes and diabetic nephropathy in type 1 diabetes, in mostly European-derived populations. RESEARCH DESIGN AND METHODS A comprehensive association analysis of 24 single-nucleotide polymorphisms (SNPs) in the adiponectin gene was performed for type 2 diabetes and(More)
We present a methodology to generate input stimulus for design validation using GoldMine, an automatic assertion generation engine that uses data mining and formal verification. GoldMine mines the simulation traces of a behavioral Register Transfer Level (RTL) design using a decision tree based learning algorithm to produce candidate assertions. These(More)
We propose a methodology to generate input stimulus to achieve coverage closure using GoldMine, an automatic assertion generation engine that uses data mining and formal verification. GoldMine mines the simulation traces of a behavioral register transfer level (RTL) design using a decision tree based learning algorithm to produce candidate assertions. These(More)
Machine learning techniques are widely employed for automatic assertion generation in hardware verification. Our previous method [16] uses a decision tree based approach for mining assertions and does not have design coverage related feedback. The assertions are unaware of the design, over-constrained and have low expressiveness. We introduce a coverage(More)