Lingxiang He

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  • Zhun Zhang, Wei He, +4 authors Jianmin Cao
  • 2016 13th IEEE International Conference on Solid…
  • 2016
This paper presents a novel hardening triple-well design for an six-transistors CMOS memory cell fabricated in 65 nm feature size. The new approach calculates the effects of single event transient (SET) with junction currents, which is derived based on device physics. Simulation presents that charge collection can be effectively mitigated with the use of(More)
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