Lina Sawalha

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Single-ISA heterogeneous (also known as asymmetric) multicore processors offer significant advantages over homogenous multicores in terms of both power and performance. Power-efficient cores can be paired with higher-performance cores to achieve advantageous power/performance tradeoffs. Unfortunately, such processors also create unique challenges in(More)
Heterogeneous multicore processors (HMPs) offer promise for significant efficiency improvement. Power-effcient cores can be paired with higher performance cores in an HMP to achieve a beneficial design in terms of both power and performance. However, such processors produce challenges in the effective mapping of threads to cores. An application could have(More)
Heterogeneity in multicore processor systems creates challenges in effectively mapping processes to diverse cores. While most approaches require programmer partitioning between core types or permutation of thread schedules to find the optimal mapping, we introduce a new machine learning approach to automated thread assignment. We train a reinforcement(More)
Heterogeneous multicore processors (HMPs) can provide better performance and reduced energy consumption than homogeneous ones [3]. Differences between cores provide different processing capabilities for different applications; a dynamic scheduler can exploit these differences to maximize performance and minimize energy consumption [5, 6] by adapting to fine(More)
The significance of computer architecture simulators in advancing computer architecture research is widely acknowledged. Computer architects have developed numerous simulators in the past few decades and their number continues to rise. This paper explores different simulation techniques and surveys many ×86 simulators. Comparing simulators with each(More)
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