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We i n troduce event-recording automata. An event-recording automaton is a timed automaton that contains, for every event a, a c l o c k that records the time of the last occurrence of a. The class of event-recording automata is, on one hand, expressive enough to model ((nite) timed transition systems and, on the other hand, determinizable and closed under(More)
In this paper we describe the ForSpec Temporal Logic (FTL), the new temporal property-specification logic of ForSpec, Intel's new formal specification language. The key features of FTL are as follows: it is a linear temporal logic, based on Pnueli's LTL, it is based on a rich set of logical and arithmeti-cal operations on bit vectors to describe state(More)
In chip multiprocessors (CMPs), limiting the number of offchip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for <i>constructive</i> cache sharing, in which concurrently scheduled threads share a largely overlapping working set. In this paper, we compare the performance of two state-of-the-art schedulers(More)
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to a correctness query with a counterexample to the satisfaction of the specification in the system. On the other hand, when the answer to the correctness query is positive, most model-checking tools provide no witness for the satisfaction of the(More)
Apoptosis is a controlled form of cell death that serves as a molecular point of regulation for biological processes. Cell selection by apoptosis occurs during normal physiological functions as well as toxicities and diseases. Apoptosis is the counterpart and counterbalance to mitosis in cell population determination. Complex patterns of cell signaling and(More)
Runtime monitoring tools are invaluable for detecting various types of bugs, in both sequential and multi-threaded programs. However, these tools often slow down the monitored program by an order of magnitude or more [4], implying that the tools are ill-suited for always-on monitoring of deployed code. Fortunately, the emergence of chip multiprocessors as a(More)
One method of handling the computational complexity of the verification process is to combine the strengths of different approaches. We propose a hybrid verification technology combining symbolic trajectory evaluation with either symbolic model checking or SAT-based model checking. This reduces significantly the cost (both human and computing) of verifying(More)
Our experience with semi-exhaustive verification shows a severe degradation in usability for the corner-case bugs, where the tuning effort becomes much higher and recovery from dead-ends is more and more difficult. Moreover, when there are no bugs at all, shifting semi-exhaustive traversal to exhaustive traversal is very expensive, if not impossible. This(More)