Lili He

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The goal of this project is to implement a 10-bit segmented current steering TSMC 0.25µm CMOS digital to analog converter. Binary coded 10-bit data was input to the converter. The converter will convert all combinations of ten bits from digital form into correspondent " staircase " voltage levels. A low pass filter placed after the output terminal of the(More)
A phase lock loop is a closed-loop system that causes one system to track with another. More precisely, a PLL can be perceived as a circuit synchronizing an output signal with a reference or input signal in frequency as well as phase. High-performance phase lock loops are widely used within a digital system for clock generation, timing recovery, and to(More)
This paper presents the design and implementation of a 6 Gbps clock and data recovery (CDR) system for Serial Advanced Technology Attachment (SATA) standard. The CDR incorporates half rate phase detector and is realized using a 2 loop PLL consisting of a coarse loop and a fine loop. Fast frequency acquisition is acquired through coarse loop and fine phase(More)
State of art phase locked loop (PLL) design methodologies and techniques are always of many mixed-signal circuit designers' interests. In this paper, a fully differential PLL having good common-mode noise rejection (low phase noise) has been designed and demonstrated using TSMC 0.25µm CMOS technology. The design and demonstration included a dead zone(More)
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