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The goal of this project is to implement a 10-bit segmented current steering TSMC 0.25µm CMOS digital to analog converter. Binary coded 10-bit data was input to the converter. The converter will convert all combinations of ten bits from digital form into correspondent " staircase " voltage levels. A low pass filter placed after the output terminal of the(More)
A phase lock loop is a closed-loop system that causes one system to track with another. More precisely, a PLL can be perceived as a circuit synchronizing an output signal with a reference or input signal in frequency as well as phase. High-performance phase lock loops are widely used within a digital system for clock generation, timing recovery, and to(More)
This paper presents the design and implementation of a 6 Gbps clock and data recovery (CDR) system for Serial Advanced Technology Attachment (SATA) standard. The CDR incorporates half rate phase detector and is realized using a 2 loop PLL consisting of a coarse loop and a fine loop. Fast frequency acquisition is acquired through coarse loop and fine phase(More)
This paper describes an 8-bit, 10 MSamples/second analog to digital converter, with 2V fully differential input range, which is implemented in TSMC 0.25µm CMOS technology. It achieves low power dissipation of 25mW, and the chip area is 0.56mm 2. Measured performance yields a very good VTC curve and a sine wave fitting curve for 200KHz input at 10Msample/s,(More)
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