Learn More
In heterogeneous multi-core systems, the scheduling overhead increases as the number of processor cores increasing. To improve the scheduling efficiency, a hardware scheduler is designed to assist the task scheduling for synergistic core in heterogeneous multi-core architecture in this paper, which support first come first served (FCFS) and dynamic priority(More)
It’s a promising way to improve performance significantly by adding reconfigurable processing unit to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. The Reconfigurable Logic is logically divided into Reconfigurable Processing Units (RPUs),(More)
For digestion of starch in humans, α-amylase first hydrolyzes starch molecules to produce α-limit dextrins, followed by complete hydrolysis to glucose by the mucosal α-glucosidases in the small intestine. It is known that α-1,6 linkages in starch are hydrolyzed at a lower rate than are α-1,4 linkages. Here, to create designed slowly digestible(More)
As the rapidly development of embedded systems, it is a challenge for universities to fill the gap between education and industry. In this paper, we introduce the experiment designed for embedded system curriculum based on embedded IA first, and then adapt the design to the new promising processor-Atom¿ - developed by Intel. At last, we will share our(More)
Network on Chip (NoC) is considered as the promising diagram of interconnection mechanism for future chip multiprocessors. As the number of processing elements (PE) on chip keeps growing, the delay for simultaneous memory references of these PEs is emerging as a serious bottleneck on high performance. One major part of this delay is from the Memory(More)
Attaching a reconfigurable loop accelerator to a processor for improving the performance and the efficiency of the system, which can be further enhanced by unrolling the loop to change its parallelism in a better way, is a promising development. The more a loop is unrolled, the wider the reconfigurable area that is exposed. However, the utilization of a(More)
Reconfigurable computing based on FPGAs (Field Programmable Gate Arrays) has been a promising solution to improve the performance with high flexibility. However, the physical capacity limitation of FPGAs prevents its wide adoption in real world. In this paper, a homogeneous NoC-based FPGA architecture is proposed, in which reconfigurable and I/O resources(More)