Lijiang Gao

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
A fast-locking digital delay-locked loop (DLL) is presented in this paper. By adopting a novel high resolution Time-to-Digital Converter (TDC), the time for generating fine-tuned codes is reduced to two clock cycles. Thus the total locking time is greatly reduced to 8 input reference clock cycles and remarkably shortened by 80% to 94.6% compared to previous(More)
  • 1