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- Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu
- IEEE Transactions on Computer-Aided Design of…
- 2008
Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices… (More)
- Pei-Wen Luo, Chun Zhang, +6 authors Yiyu Shi
- ISPD
- 2013
Power integrity is generally considered to be one of the major bottlenecks hindering the prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density and smaller… (More)
- Yi-Hsuan Lee, Yu-Min Lee, Liang-Chia Cheng, Yen-Tang Chang
- 2012 4th Asia Symposium on Quality Electronic…
- 2012
As VLSI techniques are getting more and more advanced, the size of the power grid network increases dramatically. Therefore, the power grid analysis becomes a challenging task during the design… (More)
- Tay-Jyi Lin, Cheng-An Chien, +15 authors Jinn-Shyan Wang
- 2013 IEEE International Solid-State Circuits…
- 2013
This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with… (More)
- Bing-Chuan Bai, Chun-Lung Hsu, +5 authors Chien-Mo James Li
- 2013 22nd Asian Test Symposium
- 2013
Rnv8T nonvolatile SRAM combines conventional SRAM and resistive RAM to provide both fast access speed and data retention. Traditional test methods for conventional SRAM or resistive RAM are not… (More)
- Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng
- ISPD
- 2014
The power grid needs to be frequently analyzed during the design process of power distribution network. Hence, an effective method being able to capture its transient behavior is desired for… (More)
- Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi
- 17th Asia and South Pacific Design Automation…
- 2012
Power supply noise has become one of the primary concerns in low power designs. To ensure power integrity, designers need to make sure that voltage droop and bounce do not exceed noise margin in all… (More)
- Jyu-Yuan Lai, Chih-Tsun Huang, +4 authors Juin-Ming Lu
- 2014 27th IEEE International System-on-Chip…
- 2014
Developing embedded parallel applications efficiently in modern single-chip many-core architectures is challenging. We present a novel methodology to facilitate crucial issues of parallel software… (More)
- Chen-An Chen, Yee-Wen Chen, +4 authors Liang-Chia Cheng
- 2013 22nd Asian Test Symposium
- 2013
This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the… (More)
- Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi
- IEEE Transactions on Computer-Aided Design of…
- 2016
Runtime noise management systems typically rely on on-chip noise sensors to accurately capture voltage emergencies. As such, the threshold voltage for noise sensors to report emergencies serves as a… (More)