Liang-Chia Cheng

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Yiyu Shi16
Pei-Wen Luo10
Jinjun Xiong8
Lei He7
Tao Wang7
14Yiyu Shi
12Pei-Wen Luo
5Dingjuan Chua
5Yongfu Li
5Yong Lian

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Publication Year

2007
2017

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Co-author

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Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits
Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit… (More)
Benchmarking for research in power delivery networks of three-dimensional integrated circuits
Power integrity is generally considered to be one of the major bottlenecks hindering the prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density and smaller footprint result in significantly increased power density, which threatens the system reliability. In view of this, there has been groundswell of interest in… (More)
Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs)
Three-dimensional integrated circuits (3D ICs) have drawn groundswell of interest in both academia and industry in recent years. However, the power integrity of 3D ICs is threatened by the increased current density brought by vertical integration. To enhance reliability, the locations of power/ground through-silicon-vias (P/G TSVs), which are used to… (More)
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction
Power supply noise has become one of the primary concerns in low power designs. To ensure power integrity, designers need to make sure that voltage droop and bounce do not exceed noise margin in all possible scenarios. Since it is very difficult to capture the exact worst corner among the mist of complex functionalities in modern VLSI designs, statistical… (More)
Characterization of Supply and Substrate Noises in CMOS Digital Circuits
The biggest contributors to the substrate noise are supply noises, since the power and ground wires are directly connected to the silicon substrate for CMOS digital cells. Clock trees in large digital designs can acquire large power consumption when thousands of flip-flops transitioning through the switching zone. Memories also draw significant… (More)