Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices… (More)
Power integrity is generally considered to be one of the major bottlenecks hindering the prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density and smaller… (More)
As VLSI techniques are getting more and more advanced, the size of the power grid network increases dramatically. Therefore, the power grid analysis becomes a challenging task during the design… (More)
This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with… (More)
Rnv8T nonvolatile SRAM combines conventional SRAM and resistive RAM to provide both fast access speed and data retention. Traditional test methods for conventional SRAM or resistive RAM are not… (More)
The power grid needs to be frequently analyzed during the design process of power distribution network. Hence, an effective method being able to capture its transient behavior is desired for… (More)
Power supply noise has become one of the primary concerns in low power designs. To ensure power integrity, designers need to make sure that voltage droop and bounce do not exceed noise margin in all… (More)
Developing embedded parallel applications efficiently in modern single-chip many-core architectures is challenging. We present a novel methodology to facilitate crucial issues of parallel software… (More)
This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the… (More)
Runtime noise management systems typically rely on on-chip noise sensors to accurately capture voltage emergencies. As such, the threshold voltage for noise sensors to report emergencies serves as a… (More)