• Publications
  • Influence
Dynamic voltage scaling with links for power optimization of interconnection networks
TLDR
In this paper we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. Expand
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C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
TLDR
We present a lossless compression algorithm that has a number of novel features tailored for this application, including combining pairs of compressed lines into one cache line. Expand
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Dynamic power consumption in Virtex™-II FPGA family
TLDR
This paper analyzes the dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) by taking advantage of both simulation and measurement. Expand
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System-level reliability modeling for MPSoCs
TLDR
The reliability of multi-processor systems-on-chip (MPSoCs) is affected by several inter-dependent system-level and physical effects. Expand
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ARIEL: automatic wi-fi based room fingerprinting for indoor localization
TLDR
We present ARIEL, a room localization system that automatically learns room fingerprints based on occupants' indoor movements. Expand
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Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
TLDR
We investigate the 3D CMP run-time thermal management problem and propose an efficient proactive continuously engaged hardware and operating system thermal management technique governed by optimal thermal management polices. Expand
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Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems
TLDR
We propose a novel design-time thermal optimization framework based on a temperature-aware power model. Expand
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Reliability Modeling and Management of Nanophotonic On-Chip Networks
  • Zheng Li, M. Mohamed, +8 authors Yihe Sun
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration…
  • 2012
TLDR
This paper presents an initial study of the reliability challenges of nanophotonic networks-on-chip due to fabrication-induced process variation and run-time spatial thermal variation across the die. Expand
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Thermal Modeling, Characterization and Management of On-Chip Networks
TLDR
We propose ThermalHerd, a distributed, collaborative run-time thermal management scheme for on-chip networks that uses distributed throttling and thermal-correlation based routing to tackle thermal emergencies. Expand
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HybDTM: a coordinated hardware-software approach for dynamic thermal management
TLDR
We propose HybDTM, a methodology for fine-grained, coordinated thermal management using a hybrid of hardware techniques, such as clock gating, and software techniques,such as thermal-aware process scheduling, synergistically leveraging the advantages of both approaches. Expand
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