Li-Jun Zhang

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In this paper, an integrated 512KB SRAM architecture with low power circuit design is presented. An extra Z decoding circuit is introduced, which is combined with divided wordline/bitline scheme to reduce half-selected memory cells and thus dynamic power is decreased significantly. In circuit level, we utilize source biasing scheme to achieve leakage(More)
In rapid development of digital designs, memory is the most important building block, as half of the silicon area is used to store data value and program instructions. The power consumption and speed of SRAMs are important issue that has lead to multiple designs with the purpose of minimizing the power consumption. Speed and power consumption is the key(More)
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