Lev Kirischian

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For most multi-modal stream processing tasks Dynamic Reconfigurable Systems-on-Chip (SoC) have demonstrated high efficiency in cost and power. These systems utilize partial reconfiguration for dynamic adaptation to changes in the workload or in environment. Mostly, reconfiguration mechanisms are based on central resource management sub-systems deployed in a(More)
Dynamic Partially Reconfigurable Computing(DPRC) systems have received significant attention in recent years as a potential alternative to traditional computing system designs; such systems implement much of their functionality in the form of virtual components, represented by configuration bit-streams. However, for such systems to be adopted as viable(More)
This paper presents an approach for development of cost-effective hardware platform for video/image processing. The approach utilizes the SRAM based reconfigurable logic devices (FPGAs) and, their capability of run-time temporal partitioning of logic resources. We propose the architecture for multi-mode video-stream processor with cyclically reconfigurable(More)
In this paper we present a concept of the self-assembling micro-architectures of Application Specific Virtual Processors for data-stream processing. The procedure for micro-architecture assembling is developed for Xilinx "Virtex" FPGA devices. It is shown that proposed approach allows a minimization of system resources for multi-task data-stream workload(More)
This paper presents an approach for development of cost-effective custom video/image processing systems. The approach utilizes the concept of temporal partitioning of resources in the partially reconfigurable FPGA devices. Paper proposes architecture of the multi-mode video-stream processor with cyclically reconfigurable structure. The cost-effectiveness of(More)
− When testing an analog-to-digital converter (ADC) by automatic test equipment (ATE), the latter is capable of performing extensive processing of output responses of the ADC. This allows detection of virtually any fault. However, the cost of ATE is quite high. As well, the external bandwidth of ATE is normally lower than the internal bandwidth of the ADC(More)