Leonel Tedesco

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Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies(More)
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint(More)
The major part of the state of art routing proposals have a limited view of the NoC congestion, since each router takes decisions based on few neighbors' status. Such local decision may lead packets to other congested regions, therefore being inefficient. The goal of this work is to propose and evaluate an adaptive source routing algorithm, where the path(More)
The network on chip (NoC) design process requires an adequate characterization of the application running on it to optimize communication resources utilization and dimensioning. The traffic modeling process is the most essential step for characterizing complex applications. It is possible to identify three methods to model traffic in NoC literature. The(More)
Applications executing in current MPSoCs present traffic behavior with different characteristics in terms of QoS requirements and traffic modeling. Another important MPSoC traffic feature is its unpredictability and dynamic nature. Networks-on-chip (NoCs) are communication structures being used due to higher degree of parallelism, fault tolerance, and(More)
The development of MPSoCs targeting embedded systems with a dynamic workload of applications constitutes an important challenge. The growing number of applications running on these systems produces a considerable utilization of resources, implying a high demand of computation and communication in the different MPSoC parts. The heterogeneity of processing(More)
Networks on chip (NoCs) are communication infrastructures that offer parallelism and scalability. Most NoC designs employ wormhole packet switching, since this switching mode optimizes the use of NoC resources. However, this mode may introduce jitter, possibly producing packet loss, due to the violation of temporal QoS constraints. One technique to deal(More)
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