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In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times.With the increasing complexity of designs, the traditional separation of logic and physical design leads to(More)
This paper describes the effects of false loops caused by TesouTce sharing. When a separate controller and data path aTe constructed, two types of false loops can be distinguished: the ones that go through the controller and the ones that loop around in the data path. The papeT describes a model to detect both types of loops during the TesouTce sharing(More)
Abstract: It is commonly expected that any correct implementation can replace its specification inside a larger design without violating the correctness of the whole design. This property (called replaceability) is automatically satisfied in the absence of don't cares because "correctness" by definition implies that specification and implementation compute(More)
Logic synthesis is the process of automatically generating optimized logic level representation from a high-level description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design time, while achieving performance objectives. This paper(More)
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to reduce both leakage as well as active power in a standard-cell library based high-performance design flow. We will discuss the design and cost issues for using different power(More)
The paper presents a data flow graph exchange standard, agreed upon and used by the partners in the ESPRIT research project ASCIS. These data flow graphs are generated from known user interface languages such as Silage, VHDL, and C, and are used to drive architectural synthesis packages and formal verification. The graph semantics are defined to offer a(More)
Standard cells have long been an excellent abstraction of technology. ASIC design styles allowed logic designers to very rapidly take advantage of major advantages in silicon technology. For the last few years however, many people have been predicting the death of ASICs. They argue that they are too difficult to design, that the gap between the process(More)