Leomar S. Rosa Júnior

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In this paper we describe a new BDD-based method to generate cell level networks with minimum length pull-up and pull-down chains. The use of disjoint NMOS and PMOS planes allows simplifications through unateness and nodes duplication leading to faster networks that respect the Lower Bound of serial switches in a transistor network (LB) [1]. A set of tricks(More)
This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of previous methods. We describe which figures of merit, including the logical effort, affect the design quality(More)
This paper presents a new methodology to generate efficient transistor networks. Transistor-level optimization consists in an effective possibility to increase design quality when generating CMOS logic gates to be inserted in standard cell libraries. Starting from an input ISOP, the proposed method is able to deliver series-parallel and non-series-parallel(More)
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