Lee Lerner

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We present an architecture for fail-silent operation of Field Programmable Gate Arrays (FPGAs) and configurable System-on-Chip (SoC) implementations. The architecture includes replication of the system function separated by a guard band region that guarantees that no single fault can allow interaction between the replicated system functions. The outputs of(More)
We describe a Built-In Self-Test (BIST) approach that was developed for the programmable Input/Output (I/O) buffers in Field Programmable Gate Arrays (FPGAs). The approach is unique when compared with previous work because the I/O buffers are tested separately from the other programmable logic in the I/O cells. The capabilities and limitations of(More)
Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This thesis does not include proprietary or classified information. Permission is granted to Auburn University to make copies of this thesis at its discretion, upon the request of individuals or(More)
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