LeRoy Winemberg

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This work studies the potential of capturing customer returns with models constructed based on multivariate analysis of parametric wafer sort test measurements. In such an analysis, subsets of tests are selected to build models for making pass/fail decisions. Two approaches are considered. A preemptive approach selects correlated tests to construct(More)
This work proposes a wafer probe parametric test set optimization method for predicting dies which are likely to fail in the field based on known in-field or final test fails. Large volumes of wafer probe data across 5 lots and hundreds of parametric measurements are optimized to find test sets that help predict actually observed test escapes and final test(More)
As process technology further scales, aging, noise and variations in integrated circuits (ICs) and systems become a major challenge to both the semiconductor and EDA industries , since a significantly increased mismatch is emerging between modeled and actual silicon behavior. Therefore , the addition of accurate and low-cost on-chip sensors is of great(More)
—With technology scaling, the deviation between predicted path delay using simulation and actual path delay on silicon increases due to process variation and aging. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lower cost compared to using external expensive measurement devices. In this paper, a novel(More)
Aging of transistors has become a major reliability concern especially when the VLSI circuits are in the nanometer regime. In this paper, we propose a novel methodology to address circuit aging in the field. On-chip aging sensor is designed to monitor transitions on functional paths capturing functional mode workload. Path delay is then accurately measured(More)
—Semiconductor industry has come to the era to rely heavily on detecting small-delay defects (SDDs) for high defect coverage of manufactured digital circuits and low defective parts per million (DPPM). Traditional timing-unaware transition-delay fault (TDF) ATPGs are proven to be inefficient in detecting SDDs. The commercial timing-aware ATPGs have been(More)
High test quality can be achieved through defect oriented testing using analog fault modeling approach. However, this approach is computationally demanding and typically hard to apply to large scale circuits. In this work, we use an improved inductive fault analysis approach to locate potential faults at layout level and calculate the relative probability(More)