Lawrence T. Pileggi

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This paper describes PRIMA, an algorithm for generating provably passive reduced order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to requiring macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. PRIMA extends the(More)
For digital system designs the propagation delays due to the physical interconnect can have a significant, even dominant, impact on performance. Timing analyzers attempt to capture the effect of the interconnect on the delay with a simplified model, typically an RC tree. For mid-frequency MOS integrated circuits the RC tree methods can predict the delay to(More)
The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are the uncertainty as to whether it is an optimistic or a(More)
This paper describes RICE, an RLC interconnect evaluation tool based upon the moment-matching teehnique of Asymptotic Waveform Evaluation (AWE). The RLC circuit moments are calculated by a path-tracing algorithm which enables the analysis of large interconnect models several thousand times faster than a circuit simulation while requiring 5 to 10 times less(More)
A compact nonlinear model order-reduction method (NORM) is presented that is applicable for time-invariant and periodically time-varying weakly nonlinear systems. NORM is suitable for model order reduction of a class of weakly nonlinear systems that can be well characterized by low-order Volterra functional series. The automatically extracted macromodels(More)
In this paper we develop a gate level model that allows us to determinethe best and worst case delay when there is dominant interconnectcoupling. Assuming that the gate input windows oftransition are known, the model can predict the worst and bestcase noise, as well as the worst and best case impact on delay. Thisis done in terms of a Ceff based gate model(More)
Process variations have a growing impact on circuit performance for today's integrated circuit (IC) technologies. The Non-Gaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever. In this paper, we present an efficient block-based statistical timing analysis approach with linear(More)
While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear (e.g. quadratic) response surface models can be utilized to capture larger scale process variations; however, such(More)