Lawrence T. Clark

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An embedded RISC microprocessor core fabricated in a six-layer metal 0.18m CMOS process implementing the ARMTM V.5TE instruction set is described. The core described is the first implementation of the Intel XScale MicroarchitectureTM. (ARM is a registered trademark of Advanced RISC Machines, Ltd.) The microprocessor core, which includes caches, memory(More)
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts both nominal delay and delay variability over a wide range of bias conditions, including sub-threshold. Excellent model scalability enables efficient mapping between process(More)
Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit(More)
A 512 x 13b ultra-low power subthreshold memory is fabricated on a 130-nm process technology. The fabricated memory is fully functional for read operation with a 190 mV power supply at 28 kHz, and 216 mV for write operation. Single bits are measured to read and write properly with VDD as low as 103 mV and 129 mV, respectively. The memory operates at a 1 MHz(More)
Static power dissipation is a concern for battery powered hand-held devices since it can substantially impact the battery life. Here, the use of reverse body bias to limit I<inf>off</inf> on the high performance, low power XScale&#8482; microprocessor core is described. The scheme utilized is amenable to implementation on a low-cost (non-triple well)(More)
Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18mm(More)
An internet protocol (IP) router determines the next hop for a packet by finding the longest prefix match. This lookup often occurs in ternary content addressable memory (TCAM), which allows bit masking of the IP address. In this paper, an internet protocol content addressable memory (IPCAM) circuit that directly determines the longest prefix match to the(More)