Lawrence F. Arnstein

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Though high-level synthesis tools seem to fit nicely into the traditional top-down VLSI design methodology in which an abstract algorithmic model is transformed into a detailed register transfer level implementation, there is an important difference between filling in the details by hand and relying on a high-level synthesis tool to do so. Unlike the(More)
A techm”que is introduced that gives an engineer greater control over the design space considered by a high level synthesis tool. This is accomplished by allowing the engineer to & insertions about temporal and structural relationships between operations in a data-jiow graph that must be reflected in any synthesized result. An engineer can use these(More)
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