Laurent Vandroux

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This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower than 10 mum. Direct bonding technology, die-to-wafer self-assembly, wafer thinning process and copper TSV process are discussed. 2 mum to 5 mum large copper TSV chains are presented with a TSV(More)
This paper presents an in-depth investigation of the electrical properties of charge trap memories with AlN based storage layers. The memory performance and reliability are studied in details and compared with the ones of a reference device using standard Si<sub>3</sub>N<sub>4</sub> as storage layer. An engineered charge trapping layer is also proposed,(More)
For the first time, we integrated 1.9 GPa eXtra-strained silicon on insulator (XsSOI) substrates in FDSOI n and pMOSFETs with gate length (L<sub>G</sub>) and width (W) down to 25 nm. Due to the high stress levels, significant I<sub>ON</sub>-I<sub>OFF</sub> improvements were obtained not only for nMOS but also for pMOS. We compared those results with the(More)
An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or patterned oxide/copper layers are used as the bonding medium. After a first thinning, a low stress high deposition rate oxide is deposited to embed the dices. A final thinning is then done to recover a(More)
As 3D packaging technologies are becoming more and more present in packaging roadmap, applications with higher requirement are rising continuously. Today, one of the main applications requiring 3D technologies is dedicated to nomadic components, including mobile phones, due to their very high compacity and integration capabilities. Those components need to(More)
In this paper, we demonstrate the first successful integration of "localized SOI" devices integrated with HfO<sub>2</sub>/TiN gate stack on dedicated areas of bulk CMOS substrates. We propose a low cost innovative approach based on the SON technology, where the buried sacrificial SiGe layer can be removed directly from the edges of the active area in a(More)
We report on the development of a metallic source and drain module for FDSOI pMOSFETs including lateral PtSi formation, Ti/TiN barrier, optimized doping conditions, controlled PtSi penetration below spacers and suitable cleaning of the PtSi surface prior to barrier deposition. Mean specific contact resistivity values lower than(More)
Localized metal bonding is one of the main drivers for 3D technology implementation as it allows high vertical interconnection densities between piled up dies. In this paper we will present the direct bonding of tungsten blanket. The copper and tungsten direct bonding will be compared in terms of bonding mechanism and temperature dependence.
This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO<sub>2 </sub> as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties.(More)
In recent years, silicon nanostructures have been investigated extensively for their potential use in photonic and photovoltaic applications. So far, for silicon quantum dots embedded in SiO(2), control over inter-dot distance and size has only been observed in multiple bilayer stacks of silicon-rich oxides and silicon dioxide. In this work, for the first(More)
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