Laurent Moss

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Simulation monitoring tools are needed in hardware/software codesign for performance debugging, model validation and hardware/software partitioning purposes. Existing tools are either hardware- or software-centric and lack integrated and seamless co-monitoring. This paper presents a system-level co-monitoring tool that can monitor the computation and(More)
Electronic System Level has brought new abstractions for designing systems, which most designers are not familiar with. The Space CodesignTM SystemC design framework allows designers to easily model hardware/software-based systems, starting from a high level model and refining down to the chip. We propose a rapid system prototyping toolset that permits(More)
Estimating the power consumption of System on Chip as early as possible in the design life cycle is important to meet the time to market requirements. For this purpose, most research is turning toward high-level models, like TLM, to estimate power earlier. This paper presents a high-level IP oriented power estimation methodology. The methodology separates(More)
This paper presents an Electronic System Level (ESL) framework for the system specification, hardware/software (HW/SW) co-design and rapid design space exploration of electronic systems subject to Quality of Results (QoR) constraints such as performance, area and power. This framework is based on recent standards such as SystemC TLM-2.0 and IEEE 1685(More)
This paper reports the results of a project funded by ESA on the use and development of TASTE (The ASSERT Set of Tools for Engineering). TASTE is a set of tools which, ruled by a clear methodology, aims to ease and secure the building of Real-Time Embedded (RTE) systems. The first goal of this project was to evaluate TASTE with an industrial case study, the(More)
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