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This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower than 10 mum. Direct bonding technology, die-to-wafer self-assembly, wafer thinning process and copper TSV process are discussed. 2 mum to 5 mum large copper TSV chains are presented with a TSV(More)
3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance(More)
After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard(More)
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (V<sub>TH</sub>) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable V<sub>TH</sub>. This ability can be exploited to design SRAMs cells with(More)
Germanium MOSFET is considered as a promising alternative to silicon due to its intrinsically higher carrier mobility, especially for holes. Using appropriate channel and pocket implants, this paper presents for the first time well-behaved short channel devices characteristics featuring a negative V<sub>th</sub> and no parasitic conduction at the BOx(More)
Since the end of the last millenium, the microelectronics industry is facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS devices structure or if new devices architectures are implemented. The demand for low voltage, low power and high performance are the great(More)
A number of people who use SET Die / Flip-Chip Bonders helped develop and prepare the SET Technical Bulletin: Die Bonding Applications. We would like to express our deep appreciation to all the contributing authors, all experts in their respective fields, for their many helpful suggestions and their cooperation in responding to requests for revisions. We(More)
The dynamics of domains stability of a 120-nm-thick Z-cut single-crystal LiTaO<inf>3</inf> thin film obtained through the Smart Cut&#x2122; technology is investigated using Piezoresponse Force Microscopy. The artificially created &#x2212;Z domains were found to completely relax, driven by the large built-in field observed in the structure. A constant domain(More)
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