Lasse Lehtonen

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— This paper presents a set of 9 application traffic models for benchmarking Networks-on-Chip designs. Common benchmarks allow fair comparison, reproduction of research results, and accelerate NoC development. The set is based on real applications found in literature and executable on freely available benchmarking tool called Transaction Generator (TG). It(More)
This paper presents a software-based implementation for the MIMO transmitter baseband processing conforming to the IEEE802.11ac standard on a DSP core with vector extensions. The transmitter is implemented in four different transmission scenarios, which include 2×2 and 4×4 MIMO configurations, yielding beyond 1Gbps transmit bit rate. The implementation is(More)
BACKGROUND The rapid expansion in the use of electronic health records (EHR) has increased the number of medical errors originating in health information systems (HIS). The sociotechnical approach helps in understanding risks in the development, implementation, and use of EHR and health information technology (HIT) while accounting for complex interactions(More)
—This paper analyses the effects of Network-on-Chip (NoC) models written in SystemC on simulation speed. Two Register Transfer Level (RTL) models and Approximately Timed (AT) and Loosely Timed (LT) Transaction Level (TL) models are compared against reference RTL VHDL 2D mesh model. Three different mesh sizes are evaluated using a commercial simulator and(More)
Sound and timely scientific advice is an essential requirement for the Commission to pursue modern, responsive and sustainable health systems. To this end, the Commission has set up a multidisciplinary and independent Expert Panel which provides advice on effective ways of investing in health (Commission Decision 2012/C 198/06). The core element of the(More)
Today's Multi-Processor System-on-Chips incorporate Network-on-Chips to interconnect multiple processors , memories, and accelerators. We present a freely available toolset to monitor and analyze these networks. Internal signals are pre-analyzed on FPGA without interfering the system. Host PC carries out further analysis with post-processing algorithms and(More)