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Partitioning of circuit netlists is important in many phases of VLSI design, ranging from layout to testing and hardware simulation. The ratio cut objective function [29] has received much attention since it naturally captures both min-cut and equipartition, the two traditional goals of partitioning. In this paper, we show that the second smallest(More)
We present a genetic circuit partitioning algorithm that integrates the Metis graph partitioning package 155 originally designed for sparse matrix computations. Metis is an extremely fast iterative partitioner that uses multilevel clustering. We h a ve adapted Metis to partition circuit netlists, and have applied a genetic technique that uses previous Metis(More)
In this paper, we demonstrate that the 'dual " intersection graph of the netlist strongly captures circuit properties relevant to partitioning. We apply this transformation within an existing testbed that uses an eigenvector computation to den " ve a linear ordering of nets, rather than modules [12]. We then jind a good module partition with respect to the(More)
Iterative improvement partitioning algorithms such as those due to Fiduccia and Mattheyses FM 22 and Krishnamurthy 55 exploit an eecient gain bucket data structure in selecting modules that are m o v e d f r om one partition to the other. In this paper, we investigate three gain bucket implementations and their eeect on the performance of the FM(More)
VLSI netlist partitioning has been addressed chieey by iterative methods (e.g. Kernighan-Lin 21] and Fiduccia-Mattheyses 13]) and spectral methods (e.g. Hagen-Kahng 14]). Iterative methods are the de facto industry standard, but suuer diminished stability and solution quality when instances grow large. Spectral methods have achieved high-quality solutions,(More)
We show how to quantify the suboptimality of heuristic algorithms for NP-hard problems arising in VLSI layout. Our approach is based on the notion of constructing new scaled instances from an initial problem instance. From the given problem instance, we essentially construct doubled, tripled, etc. instances which have optimum solution costs at most twice,(More)
The complexity of circuit designs has necessitated a top-down approach to layout synthesis. A large body of work shows that a good partitioning hierarchy, as measured by the associated Rent parameter, will correspond to an area-eecient layout. We deene the intrinsic Rent parameter of a netlist to be a lower bound on the Rent parameter of any partitioning(More)