Lars Hedrich

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We present a new methodology for current driven routing and layout verification for analog applications used to avoid defects due to electromigration. The methodology presented uses a commercial simulator to calculate the current flow at all terminals of the analog circuit. Afterwards maximum currents per terminal are extracted and used as guidance for the(More)
a circuit with tolerance parameter fulfills a certain specification for all parameter combinations, because the tolerance parameters are modelled with a probabilistic density function, or the computed regions are non pessimistic approximations like convex polyhedrons. In contrast to the above, the proposed approach deals with intervals, enabling an exact(More)
We present a novel approach to optimization-based variation-tolerant analog circuit sizing. Using formal methods based on affine arithmetic, we calculate guaranteed bounds on the worst-case behavior and deterministically find the global optimum of the sizing problem by means of branch-and-bound optimization. To solve the nonlinear circuit equations with(More)
In this contribution we present algorithms for model checking of analog circuits enabling the specification of time constraints. Furthermore, a methodology for defining time-based specifications is introduced. An already known method for model checking of integrated analog circuits has been extended to take into account time constraints. The method will be(More)
The paper presents an overview of a major research project on dependable embedded systems that has started in Fall 2010 and is running for a projected duration of six years. Aim is a 'dependability co-design' that spans various levels of abstraction in the design process of embedded systems starting from gate level through operating system, applications(More)
In this contribution an advanced methodology for model checking of analog systems is introduced. A new Analog Specification Language (ASL) for efficient property specifications is defined and model checking algorithms for implementing this language are presented. This allows verification of complex static and dynamic circuit properties like Oscillation and(More)