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Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability.(More)
Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit(More)
We present Output Prediction Logic (OPL), a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2X to 3 X over (optimized) conventional static CMOS are demonstrated for a variet),(More)
Existing static timing analyzers make several assumptions about circuits, implicitly trading off accuracy for speed. In this paper we examine the validity of these assumptions, notably the slope approximation to waveforms, single-input transitions, and the choice of a propagating signal based on a single voltage-time point. We provide data on static CMOS(More)
The interactive design of parametric curves and surfaces places a tremendous computational burden on general-purpose workstations. We describe two architectures for a VLSI co-processor chip that generates a large class of spline descriptions extremely quickly. This architecture is based on a generalization of the de Casteljau algorithm for Bézier curves and(More)
Teaching students the complete process of circuit design, simulation, implementation, test and debug is a daunting task. Even though design description tools and circuit compilers have kept up with the increasing levels of integration found in current implementation media such as FPGAs and microcontrollers, it has become increasingly difficult for students(More)
Ideally, the development phase of a new FPGA architecture would make use of a reliable set of mapping tools to produce accurate performance evaluations of proposed designs. Unfortunately, given the quick production time frames faced by most developers, tool construction is often postponed until after many architectural features have been frozen. To satisfy(More)
We present a fast 64b adder based on output prediction logic (OPL) that has a measured worst-case delay of 409ps, equivalent to 4.7 FO4 inverter delays for the TSMC 0.18/spl mu/m process that was used for fabrication. This normalized delay is 1.45X faster than the fastest previously reported 64b adder. The adder uses a modified radix-3 Kogge-Stone(More)