Larry L. Biro

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Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz. This paper describes some of the techniques the Alpha design team utilized(More)
The circuit techniques used to implement a 600MHz, out-of-order, superscalar RISC Alpha microprocessor are described. Innovative logic and circuit design created a chip that attains 30+ SpecInt95 and 50+ SpecFP95, and supports a secondary cache bandwidth of 6.4GB/s. Microarchitectural techniques were used to optimize latencies and cycle time, while a(More)
The NVAX and NVAX+ CPU chips are high-performance VAX microprocessors that use techniques traditionally associated with RISC microprocessor designs to dramatically improve VAX performance. The two chips provide an upgrade path for existing VAX systems and a migration path from VAX systems to the new Alpha AXP systems. The design evolved throughout the(More)
Static timing verification on a large full-custom design is an extremely challenging problem for which no complete solution exists. In this paper, we present our experience on the timing verification of our next generation CMOS CPU design using an internally developed tool, NTV. The entire chip, which consists of 1.2M transistors and 500K nodes, has been(More)
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