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Mixed-signal testing is becoming an important issue that affects both the time-to-market and product cost of many SoCs. This paper presents an effective Built-in Self-Test (BIST) method of Charge-Pump Phase-Locked Loops (CP-PLL) which is a mixed-signal circuit widely used in most of SoCs. This BIST will use the existing circuits units as test device in the(More)
To ensure qualification of charge-pump locked-loop (CP-PLL), a complete built-in self-test (BIST) scheme should provide functions of measurement of the clock jitter and detection of faults in CP-PLL. This paper proposes a low cost BIST structure providing both the faults detected and timing jitter measured. The structure based on the proposed(More)
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