Lakshmi P. Rao

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This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5–13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5(More)
Analog discrete-time finite-impulse-response (FIR) filters have been used as equalizers in digital communication receivers. For high speed applications, an FIR equalizer can be implemented using parallel sample-and-holds (S/Hs) and time-interleaved equalizer channels. Mismatches among the parallel S/Hs degrade the equalizer performance. This paper addresses(More)
This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5-13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5(More)
This paper describes an 8.5-11.5 Gb/s transceiver with a dual path receiver and a voltage-mode transmitter. The RX can operate either in ADC mode for complex loss channels such as optical multimode fiber or in DFE mode for copper-based backplane links. The ADC path implements a 2X interleaved 6-bit rectifying flash ADC using a programmable gain amplifier(More)
In an analog discrete-time circular buffer forward equalizer (FE), finite bandwidth in the sample-and-hold (S/H) circuit can introduce significant intersymbol interference (ISI) that degrades the FE performance. This brief investigates the effect of the finite S/H bandwidth and presents two methods to equalize the ISI introduced by the finite S/H bandwidth.(More)
In a conventional analog adaptive forward equalizer (FE), parasitic capacitance introduces an undesired RC pole at the output node of the equalizer. At high data rates, this pole can introduce intersymbol interference (ISI) that degrades performance. This paper considers the effect of the parasitic pole and presents two approaches to deal with the parasitic(More)
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