Lahoucine Idkhajine

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Real-time simulation of Power Electronic Converters (PECs) allows a first realistic validation of their digital controllers and avoids experimental constrains (cost, damage risks, reliability ...). However, to increase the realism of validation, the real-time model has to reach a high level of accuracy. This objective is balanced by, among others, the(More)
The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools.(More)
This paper aims to provide Hardware/Software (Hw/Sw) codesign guidelines for system-on-chip field-programmable gate array-based sensorless ac drive applications. Among these guidelines, an efficient Hw/Sw partitioning procedure is presented. This Hw/Sw partitioning is performed taking into account both the control requirements (bandwidth and stability(More)
This paper presents a short state-of-the-art Field Programmable Gate Array (FPGA) technology. An efficient design methodology for designing FPGA-based controllers is also described. To illustrate the interest of this methodology, a complex sensorless algorithm for AC drives has been chosen. It consists in an Extended Kalman Filter (EKF), which is most of(More)
This paper presents a Field Programmable Gate Array (FPGA) based Sensorless current controller for a Salient Synchronous Machine (SSM). The implemented algorithm uses an Extended Kalman Filter (EKF) to estimate the rotor position. The used FPGA design methodology has been presented including functional simulations, development of the FPGA architecture and(More)
This paper presents the implementation of a current control for synchronous machine using the fusion field programmable gate array (FPGA) from Actel Company. This component integrates analog peripherals such as ADC and also flash memory blocks, in a single chip. The achieved implementation allows evaluating the efficiency and the integration capacity of a(More)