LaNae J. Avra

Learn More
We present a new output encoding problem as follows: Given a specification table, such as a truth table or a finite state machine state table, where some of the outputs are specified in terms of 1's, 0's and don't cares, and others are specified symbolically, and assuming that the minimum number of bits are used to encode the symbolic outputs(More)
The multiplexer is a common standard sub-circuit used frequently in the datapath logic of complex designs, typically to provide a path for routing operands to operations and operation results to destination registers. During RTL synthesis, multiplexers are used for realizing ifthen-else and case statements in the RTL design description. In this paper, we(More)
A methodology for automatically synthesizing a testable RTL (register-transfer-level) hardware specification from a behavioral VHDL (VHSIC hardware description language) specification is presented. Behavioral synthesis is described. It consists of the automatic creation of a hardware specification, given an input specification that describes how the(More)