Learn More
A methodology for automatically synthesizing a testable RTL (register-transfer-level) hardware specification from a behavioral VHDL (VHSIC hardware description language) specification is presented. Behavioral synthesis is described. It consists of the automatic creation of a hardware specification, given an input specification that describes how the(More)
We present a new output encoding problem as follows: Given a specification table, such as a truth table or a finite state machine state table, where some of the outputs are specified in terms of 1's, 0's and don't cares, and others are specified symbolically, and assuming that the minimum number of bits are used to encode the symbolic outputs(More)
This report introduces new design and synthesis techniques that reduce the area and improve the performance of embedded built-in self-test (BIST) architectures such as circular BIST and parallel BIST. Our goal is to arrange the system bistables into scan paths so that some of the BIST and scan logic is shared with the system logic. Logic sharing is possible(More)
Hardware synthesis techniques automatically generate a structural hardware implementation given an abstract (e.g., functional, behavioral, register transfer) description of the behavior of the design. Existing hardware synthesis systems typically use cost and performance as the main criteria for selecting the best hardware implementation, and seldom even(More)