• Publications
  • Influence
Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet
TLDR
This paper examines the research decisions and design tradeoffs that arise when applying wireless peer-to-peer networking techniques in a mobile sensor network designed to support wildlife tracking for biology research. Expand
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DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
TLDR
We present DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks. Expand
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GARNET: A detailed on-chip network model inside a full-system simulator
TLDR
We developed a detailed cycle-accurate interconnection network model (GARNET), inside the GEMS full-system simulation framework. Expand
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ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
TLDR
We developed ORION 2.0, an extensive enhancement of the original NoC power models which includes completely new subcomponent power models, area models, as well as improved and updated technology models. Expand
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A delay model and speculative architecture for pipelined routers
  • L. Peh, W. Dally
  • Computer Science
  • Proceedings HPCA Seventh International Symposium…
  • 20 January 2001
TLDR
This paper introduces a router delay model that accurately models key aspects of modern routers. Expand
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Orion: a power-performance simulator for interconnection networks
TLDR
We present Orion, a power-performance interconnection network simulator that is capable of providing detailed power characteristics, in addition to performance characteristics, to enable rapid power performance tradeoffs at the architectural-level. Expand
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Dynamic voltage scaling with links for power optimization of interconnection networks
TLDR
In this paper we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. Expand
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Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
TLDR
We propose Virtual Circuit Tree Multicasting (VCTM) and present a detailed multicast router design that improves network performance by up to 90% while reducing network activity (hence power) by 53%. Expand
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Research Challenges for On-Chip Interconnection Networks
TLDR
On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SoCs common in consumer embedded systems, the National Science Foundation initiated a workshop that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field. Expand
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Breaking the on-chip latency barrier using SMART
TLDR
We propose an on-chip network called SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) that aims to present a single-cycle data-path all the way from the source to the destination. Expand
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