• Publications
  • Influence
Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet
TLDR
The goal is to use the least energy, storage, and other resources necessary to maintain a reliable system with a very high `data homing' success rate and it is believed that the domain-centric protocols and energy tradeoffs presented here for ZebraNet will have general applicability in other wireless and sensor applications.
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
TLDR
DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks, is presented and the results show the implications of different technology scenarios and the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature.
GARNET: A detailed on-chip network model inside a full-system simulator
TLDR
A detailed cycle-accurate interconnection network model (GARNET) is developed, inside the GEMS full-system simulation framework, that provides a detailed and accurate memory system timing model and shows that in improving on-chip network latency-throughput, EVCs do lead to better overall system runtime, however, the impact varies widely across applications.
A delay model and speculative architecture for pipelined routers
  • L. Peh, W. Dally
  • Computer Science
    Proceedings HPCA Seventh International Symposium…
  • 20 January 2001
TLDR
This paper introduces a router delay model that accurately models key aspects of modern routers and introduces a microarchitecture for a speculative virtual-channel router that significantly reduces its router latency to that of a brown hole router.
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
TLDR
The development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models, confirms the need for accurate early-stage NoC power estimation.
Dynamic voltage scaling with links for power optimization of interconnection networks
  • L. Shang, L. Peh, N. Jha
  • Computer Science
    The Ninth International Symposium on High…
  • 8 February 2003
TLDR
This paper proposes a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization that realizes up to 6.3/spl times/ power savings and is accompanied by a moderate impact on performance.
Orion: a power-performance simulator for interconnection networks
We present Orion, a power-performance interconnection network simulator that is capable of providing detailed power characteristics, in addition to performance characteristics, to enable rapid
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
TLDR
The proposed Virtual Circuit Tree Multicasting (VCTM) router is flexible enough to improve interconnect performance for a broad spectrum of multicasting scenarios, and achieves these benefits with straightforward and inexpensive extensions to a state-of-the-art packet-switched router.
Research Challenges for On-Chip Interconnection Networks
TLDR
A workshop was initiated that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field.
Breaking the on-chip latency barrier using SMART
TLDR
This work proposes an on-chip network called SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) that aims to present a single-cycle data-path all the way from the source to the destination.
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