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Basic mechanisms and modeling of single-event upset in digital microelectronics
Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historicalExpand
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Single Event Transients in Digital CMOS—A Review
The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore'sExpand
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Charge Collection and Charge Sharing in a 130 nm CMOS Technology
Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hitExpand
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Monte Carlo Simulation of Single Event Effects
In this paper, we describe a Monte Carlo approach for estimating the frequency and character of single event effects based on a combination of physical modeling of discrete radiation events, deviceExpand
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A Hardened-by-Design Technique for RF Digital Phase-Locked Loops
A RHBD topology for digital phase-locked loops (DPLLs) has been developed for single-event transient (SET) mitigation. By replacing the vulnerable current-based charge pump with a SET-resistantExpand
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Layout Technique for Single-Event Transient Mitigation via Pulse Quenching
A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive areaExpand
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Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits
Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3-D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS hasExpand
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Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs
TLDR
A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived and compared with expected upset rates for sub-100-nm SRAM memories in space environments. Expand
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  • PDF
A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit
A single-event model capable of capturing bias- dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit. Simulation comparisons withExpand
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RHBD techniques for mitigating effects of single-event hits using guard-gates
Hardening-by-design techniques to mitigate the effect of single-event transients (SET) using guard-gates are developed. Design approaches for addressing combinational logic hits and storage cell hitsExpand
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