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A Double-Stage Kalman Filter for Orientation Tracking With an Integrated Processor in 9-D IMU
TLDR
The final goal of this work is to realize an upgraded application-specified integrated circuit that controls the microelectromechanical systems (MEMS) sensor and integrates the ASIP, which will allow the MEMS sensor gyro plus accelerometer and the angular estimation system to be contained in a single package. Expand
Low Complexity LDPC Code Decoders for Next Generation Standards
TLDR
The design of low complexity LDPC codes decoders for the upcoming WiFi, WiMax and DVB-S2 standards are presented and state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. Expand
Batteries and battery management systems for electric vehicles
TLDR
A general and flexible architecture for battery management implementation and the main techniques for state-of-charge estimation and charge balancing are reported and an innovative BMS is described, which incorporates an almost fully-integrated active charge equalizer. Expand
Layered Decoding of Non-Layered LDPC Codes
TLDR
The principle of "layered decoding" is extended to those codes not especially conceived for this practice, as to benefit of the increased convergence speed, and the average boost of two times in the convergence speed is shown. Expand
Sensing Devices and Sensor Signal Processing for Remote Monitoring of Vital Signs in CHF Patients
TLDR
The proposed telemedicine platform represents a valid support to early detect the alterations in vital signs that precede the acute syndromes, allowing early home interventions thus reducing the number of subsequent hospitalizations. Expand
A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes
TLDR
The logic synthesis on 65 nm CMOS technology with low- power standard-cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 180 to 410 Mbps, and the power consumption being below 235 mW. Expand
A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes
TLDR
A scalable architecture of a decoder for IEEE 802.11n low-density parity-check (LDPC) codes is described, and a very effective technique to re- arrange the sequence of its elaborations is proposed in order to minimize the iteration latency. Expand
A multi-standard flexible turbo/LDPC decoder via ASIC design
TLDR
This paper describes the first complete design of a single-core multi-standard flexible Turbo/LDPC decoder using an ASIC approach and provides a proof-of-concept implementation complaint with 3GPP-HSDPA, DVB-SH, IEEE 802.16e and IEEE802.11n standards. Expand
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip
TLDR
This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. Expand
Low-error digital hardware implementation of artificial neuron activation functions and their derivative
TLDR
A low-error approximation of the sigmoid function and hyperbolic tangent, which are mainly used to activate the artificial neuron, are proposed based on the piecewise linear method, showing better results than the state-of-the-art. Expand
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