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In previous research interconnection was optimised when the module allocation for the operations and the register allocation for the variables already had been done. However, both the amount of multiplexing and interconnect are crucial factors to both the delay and the area of a circuit. In this paper it is shown that when variables are grouped into(More)
<italic>In this paper a computer program for the construction of a schematic diagram (the artwork) from a net list (the network) is presented. The network-to-artwork generator is composed of a separate placement (Pablo) and a routing part (Eureka). For both parts algorithms, following guidelines traditionally used in manual drawing of schematic diagrams,(More)
During the automatic generation of complex VLSI-circuits from a high level description it is necessary to provide some graphical feedback to the designer. This can be done by drawing a schematic diagram of a temporarily constructed network. To overcome the time consuming manual drawing of such diagrams, an automatic schematic diagram generator is developed.(More)
The tutorial presents an introduction into " DfY/DfM-Design for Yield and Manufacturability " covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of(More)
This paper describes optimization techniques using don't-care conditions that span the domain of high-level and logic synthesis. The following three issues are discussed: 1 how to describe and extract don't-care conditions from high-level descriptions; 2 how t o p a s s don't-care conditions from high-level to logic synthesis ; and 3 how to optimize the(More)
Logic synthesis is the process of automatically generating optimized logic-level representation from a high-level description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design time while achieving performance objectives. This paper(More)
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