L. Richard Carley

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This article describes an approach for implementing a complete computer system ~CPU, RAM, I/O, and nonvolatile mass memory! on a single integrated-circuit substrate ~a chip!—hence, the name ‘‘single-chip computer.’’ The approach presented combines advances in the field of microelectromechanical systems ~MEMS! and micromagnetics with traditional low-cost(More)
We describe a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks each with associated design knowledge. We also describe mechanisms to select from among alternate design styles, and to translate performance specifications from one level in the(More)
We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis(More)
High-speed medium-resolution ADCs are widely utilized in high-speed communication systems, such as serial links, UWB, and OFDM-based 60GHz receivers. Due to complex DSP and low-power constraints, digital basebands are designed in low-leakage, high-V<inf>T</inf> low-power (LP) CMOS processes making the design of high-speed ADCs challenging. Time-Interleaved(More)
A new approach to cell-level analog circuit synthesis is presented. This approach formulates analog synthesis as a Mixed-Integer Nonlinear Programming (MINLP) problem in order to allow simultaneous topology and parameter selection. Topology choices are represented as binary integer variables and design parameters (e.g., device sizes and bias voltages) as(More)
Analog synthesis tools have traditionally traded quality for speed, substituting simplified circuit evaluation methods for full simulation in order to accelerate the numerical search for solution candidates. As a result, these tools have failed to migrate into mainstream use primarily because of difficulties in reconciling the simplified models required for(More)
In this paper, we report a fully integrated power amplifier (PA) architecture that combines the power of 16 on-chip PAs using a 16-way zero-degree combiner to achieve an output power of 0.7W with a power-added efficiency (PAE) of 10% at 42GHz and a -3dB bandwidth of 9GHz. This is 2.6 times more output power than a recently reported millimeter-Wave (mm-Wave)(More)
A transformer-combined fully integrated outphasing class-D PA in 45 nm LP CMOS achieves 31.5 dBm peak output power at 2.4 GHz with 27% peak PAE, and supports over 86 dB of output power range. The PA employs dynamic power control (DPC) whereby sections of the PA are turned on or off dynamically according to the instantaneous signal amplitude to reduce power(More)
The increasing availability of dynamically growing digital data that can be used for extracting social networks has led to an upsurge of interest in the analysis of dynamic social networks. One key aspect of social network analysis is to understand the central nodes in a network. However, dynamic calculation of centrality values for rapidly growing networks(More)