L. Ninomiya

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The authors present a 65nm embedded DRAM cell (0.127 &#x003BC;m<sup>2</sup> cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless(More)
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