L.M. Coulibaly

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In the past, gate delay was the dominant factor in determining circuit performance. However, as feature size becomes smaller and chip area becomes larger in integrated circuits, interconnect delay has become an increasingly important factor in determining circuit performance. In this paper, we present an analytical delay calculation approach for a(More)
In today's very large scale integration (VLSI) circuits based on ultra deep submicron (DSM) process technology, on-chip interconnect plays a dominating role in determining the overall circuit performance, reliability and cost. On-chip interconnects are best modelled as a network of coupled lines. Hence, their delay estimation has to consider the effect of(More)
As feature size decreases and circuit size and complexity increases, interconnect plays a dominating role in determining the overall circuit performance, reliability and cost. With decreasing feature sizes, the delay due to the resistance and capacitance of on-chip interconnects increasingly dominates the delay due to transistors. In this paper, we present(More)
Analytical modelling of electromagnetic signatures (EMSs) for testing VLSI integrated circuits (ICs) will be considered. As crosstalk noise induced by IC interconnects is associated with a level or pattern of EMF, we approach the modelling of EM signatures by deriving an accurate analytical correlation between a given cross-talk noise voltage level and its(More)
The continuous down scaling of feature sizes into deep sub-micrometer dimensions, coupled with the used of high operation frequency in very large scale integration (VLSI) has made the on-chip interconnect the most dominant factor determining the overall circuit signal integrity performance. However, present VLSI interconnects are best modelled as(More)
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