L. C. Rodoni

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A 60 GHz cross-coupled differential LC CMOS VCO is presented in this paper, which is optimized for a large frequency tuning range using conventional MOSFET varactors. The MMIC is fabricated on digital 90 nm SOI technology and requires a circuit area of less than 0.1 mm/sup 2/ including the 50 /spl Omega/ output buffers. Within a frequency control range from(More)
In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS(More)
This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2times-oversampling phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with(More)
Introduction: The increase of transistor speed in CMOS technologies has been reached mainly by scaling the gate length of the MOS transistors. For the most advanced technologies, gate lengths down to 40 nm with an ft of 243 GHz [1] have been reported. This allows performances comparable to expensive III-V technologies based on GaAs or InP and in addition(More)
A low power consuming voltage controlled oscillator (VCO) at C-band frequencies is presented in this paper. With a supply voltage of 1.2 V and a current consumption of 1.8 mA, an output power of -3.5 dBm, an efficiency of 15 % and a phase noise of -110 dBc/Hz are achieved. Varying the tuning voltage horn 0 V to the supply voltage results in a tuning range(More)
This paper presents a quarter rate clock/data recovery (CDR) circuit for plesiochronous serial I/O-links. This 2x-oversampled phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s thanks to a data rate selection logic. A bit error rate &lt;10<sup>-12</sup> was verified up to 38 Gb/s using a(More)
A sampling latch for full-, half and quarter-rate clock and data recovery circuits at data rates of 12.5 Gb/s, 20 Gb/s and 25 Gb/s, respectively, achieving a bit error rate lower than 10<sup>-12</sup> is presented. The circuit is implemented in a 90-nm CMOS technology. The master-slave D-FF including peaking inductors consumes only 1 mW of power and(More)
The design of a travelling wave amplifier in silicon on insulator CMOS technology with operation up to 40 GHz is presented. Bulk contacts are implemented to avoid undesired memory effects. The influence of the applied bulk voltage is investigated. At 50 Omega terminations and 2 V times 38 mA supply power, a gain of more than 10 dB and 8 dB are measured up(More)
In this paper, an integrated 2-to-1 selector multiplexer in 90-nm complementary metal-oxide semiconductor (CMOS) digital technology is presented. The multiplexer is based on a differential Gilbert-cell structure. Peaking inductors are used to improve the bandwidth. At a supply voltage of 1.2 V, a speed performance of 24 Gb/s is achieved. The circuit core(More)
A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation(More)
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