Kyusun Choi

Learn More
The design methods and the automation of the compara-tor circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ) based A/D converters require 2 n , 1 comparators, each one different from all others. Optimal design method of the TIQ comparator presented in this paper significantly improves(More)
This paper presents an ultrafast CMOS flash A/D converter design and performance. Although the featured A/D converter is designed in CMOS, the performance is compatible to that of GaAs technology currently available. To achieve high-speed in CMOS, the featured A/D converter utilizes the Threshold Inverter Quantization (TIQ) technique. A 6-bit TIQ based(More)
The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the authors presented the fat tree thermometer code-to-binary code encoder that is highly suitable for the ultra-high speed flash ADCs. The simulation and the implementation results show that the fat tree encoder outperforms the commonly(More)
The proposed CMOS ultrasound transceiver chip will enable the development of portable high resolution, high-frequency ultrasonic imaging systems. The transceiver chip is designed for close-coupled MEMS transducer arrays which operate with a 3.3-V power supply. In addition, a transmit digital beamforming system architecture is supported in this work. A(More)
This paper presents a comparator generation and selection method to reduce the linearity errors-DNL and INL-for a CMOS flash analog-to-digital converter (ADC) based on threshold inverter quantization (TIQ) technique. The TIQ flash ADC requires 2 n , 1 com-parators like conventional flash ADCs. However, each comparator in the TIQ flash ADC has different(More)
A new power and resolution adaptive flash ADC, named PRA-ADC, is proposed. The PRA-ADC enables exponential power reduction with linear resolution reduction. Unused parallel voltage comparators are switched to standby mode. The voltage comparators consume only the leakage power during the standby mode. The PRA-ADC, capable of operating at 5-bit, 6-bit,(More)
This paper presents a new voltage comparator design called Quantum Voltage (QV) comparator for the next generation deep sub-micron low voltage CMOS flash A/D converter (ADC). Unlike the traditional differential voltage comparators designed to minimize input-offset voltage error due to the mismatches in a differential transistor pair, the QV comparators are(More)
A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique , a flash ADC can be applied to low supply voltage. A fat tree encoder that has signal delay of O(log2N) is used for performance. A 6-bit and an 8-bit flash ADC were designed with 0.07 µm(More)