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– This paper introduces a radically different approach to parallel simulation for gate level design, aimed at completely eliminating the communication and synchronization overhead between simulators. It is based on a new concept of temporal parallel simulation: in contrast to traditional, spatially-distributed simulation, which partitions the design into(More)
Simulation speedup offered by distributed parallel event-driven simulation is known to be seriously limited by the synchronization and communication overhead. These limiting factors are particularly severe in gate-level timing simulation. This paper describes a radically different approach to gate-level simulation based on a concept of temporal rather than(More)
Simulation-based functional verification is characterized by two inherently conflicting targets: the signal visibility and simulation performance. Achieving a proper trade-off between these two targets is of paramount importance. Even though HDL simulators are the most widely used verification platform at the RTL and gate level, their major drawback is the(More)
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