Kyu-won Choi

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In this paper, for low-power embedded systems, we solve the instruction scheduling and reordering problem as a Precedence Constrained Hamiltonian Path Problem for DAGs and the Traveling Salesman Problem (TSP), both of which are NP-Hard [1,2]. We propose an efficient instruction-level optimization algorithm for solving the NP-Hard problem. Minimum spanning(More)
In embedded systems, off-chip buses and memory (i.e., L2 memory as opposed to the L1 memory which is usually on-chip cache) consume significant power, often more than the processor itself. In this paper, for the case of an embedded system with one processor chip and one memory chip, we propose frequency and voltage scaling of the off-chip buses and the(More)
In this paper, a novel algorithm is proposed for assigning supply voltages to serially executing functional units (FUs) in a digital system such that the overall dynamic energy consumption is minimized for a given timing constraint. Novel closed form expressions for optimum supply voltage values are presented. The computation time of the algorithm is O(N)(More)
In this paper, we propose an efficient approach to minimize total power (switching, short-circuit, and leakage power) without performance loss for ultra-low power CMOS circuits in nanometer technologies. We present a framework for combining supply/threshold voltage scaling, gate sizing, and interconnect scaling techniques for power optimization and propose(More)
This paper describes an efficient hierarchical design and optimization approach for ultra-low power CMOS logic circuits. We introduce the <i>Hierarchical Activity-Aware Time Slack Distribution</i> (HA<sup>2</sup>TSD) algorithm, which distributes the surplus time slack into the most power-hungry modules hierarchically. HA<sup>2</sup>TSD ensures that the(More)
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