Kyoji Yuyama

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Placement algorithms optimizing signal delay as well as wirability for high-speed ECL masterslice LSI's are proposed. Equivalent constraints of wire length for clock skew, data path delay, and wired-OR are classified according to upper and lower limits. To maintain such limits, a top-down method utilizing an augmented two-dimensional clustering placement(More)
A tile-based datapath layout generator is proposed. MOSAIC achieves a new routing technique which uses bus patterns pre-placed all over the leaf cell and joins these segments based on module schematic information. With this routing technique, a high layout density can be achieved. Based on experience, the layout density of the 12OMHz microprocessor datapath(More)
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