Kyoichi Suguro

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The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom(More)
35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was(More)
High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with L<sub>g</sub> = 15 nm and W<sub>fin</sub> =15 nm at V<sub>d</sub>= 1.0 V and I<sub>off</sub>= 100 nA/mum.(More)
We have investigated millisecond anneal, such as laser spike annealing (LSA) and flash lamp annealing (FLA), which substitute for spike RTA as a dopant activation technology of source/drain extension for 45 nm node. Three key issues of gate leakage current, junction leakage current and pattern dependence were discussed from the integration and CMOSFETs(More)
We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10 nm fin width have been demonstrated. A new process technique for the selective gate sidewall spacer(More)
Ultra-thin nitrogen incorporated ZrO/sub 2/ (ZrON) film is successfully prepared by low temperature oxidation of ZrN. Capacitance equivalent thickness (CET) of 15 /spl Aring/ with Jg=1 mA/cm/sup 2/@ Vg=-1 V is demonstrated. There is no increase in CET up to 1000/spl deg/C. Silicide formation at poly-Si/ZrO/sub 2//Si stack at high temperature annealing is(More)
This paper presents ultra shallow junction with low resistance in 45-65nm technology node. Rapid thermal annealing is required to form ultra-shallow, low sheet resistance and lower dislocation density for satisfying the pn junction leakage specification of mobile LSIs. In order to minimize the annealing time at high temperatures, various kinds of(More)
The impact of new flash lamp annealing (FLA) technology, which both minimizes diffusion to yield a shallow junction and realizes low sheet resistivity, is investigated based on MOSFET fabrication and computer simulations. Productivity can be improved since FLA makes it possible to employ higher acceleration energy ion implantation and higher throughput. The(More)
This paper discusses the key FinFET process and integration technologies to achieve high performance LSI. Firstly, side wall pattern transfer technique is introduced to realize an aggressively scaled down FinFET with 10 nm Fin width (W<sub>fin</sub>) and 15 nm gate length (L<sub>g</sub>). Next, dopant segregation (DS) Schottky technique is demonstrated to(More)
We investigated MOS characteristics of metal gate electrodes on ultrathin gate oxide. Gate leakage currents of sputtered TiN and WN/sub x/ electrodes were found to be much higher than that of CVD TiN electrodes due to metal penetration during sputtering. Moreover, the deviation of crystal orientation of the TiN was found to affect the flat band voltage. The(More)